Scalable Design of High - Performance On - Chip Terahertz Source and Imager

In this thesis, two chip designs using the scalable array architecture are introduced. Firstly, we introduce a scalable architecture of coherent harmonic oscillator array for high-power and collimated radiation beam at mid-THz band. The array is 2Dcoupled, and each element achieves these functions: (i) maximize oscillation at fundamental frequency fo= 2 50 GHz; (ii) synchronize phase of fo and its harmonics among elements; (iii) cancel near-field radiation of fo, 2fo and 3fo, and (iv) efficiently radiate at 4fo and combine power in free space. The resultant compact design fits into the optimal radiator pitch of A/2 (half wavelength) for side-lobe suppression and enables high density implementation of THz arrays. An array prototype of 42 coherent radiators, or 91 resonant antennas, at 1 THz is also presented using IHP S13G2 130-nm SiGe process. The chip occupies 1-mm 2 area and consumes 1.1 W of DC power. The measured total radiated power and effective isotropically-radiated power (EIRP) are 80 pW and 13 dBm, respectively. Secondly, we introduce a scalable architecture of coherent receiver array for beam-steerable imaging. The array is also 2D-coupled, and each element achieves theses functions: (i) maximize oscillation at fo=120 GHz; (ii) synchronize phase of fo and its harmonics among elements; (iii) cancel radiation of fo and 2fo; and (iv) receive and down-convert RF signal near 2fo=240 GHz and output baseband signal for digital beam-forming. Chip is fabricated using TSMC 65nm LP CMOS technology. Thesis Supervisor: Ruonan Han Title: Assistant Professor of Electrical Engineering and Computer Science